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Draft:Cache memory
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11	Design of Parallel and High Performance Computing HS 2015 Torsten Hoefler, Markus P¨ uschel Department of Computer Science ETH Zurich Add to Reading List Source URL: spcl.inf.ethz.ch Language: English - Date: 2015-10-01 06:53:45 Cache coherency MESI protocol Cache False sharing Draft:Cache memory CPU cache
12	Cache Memories Marc Moreno Maza University of Western Ontario, London, Ontario (Canada) CS2101 October 2012 Add to Reading List Source URL: www.csd.uwo.ca Language: English - Date: 2014-11-03 23:52:18 Computer memory Computer architecture Cache CPU cache Central processing unit Draft:Cache memory Memory hierarchy
13	EUROPEAN PATENT OFFICE U.S. PATENT AND TRADEMARK OFFICE CPC NOTICE OF CHANGES 266 DATE: AUGUST 1, 2016 PROJECT RP0311 Add to Reading List Source URL: www.cooperativepatentclassification.org Language: English Cache Central processing unit Computer memory CPU cache Web cache Trie Draft:Cache memory
14	IEEE TRANSACTIONS ON COMPUTERS, VOL. 65, NO. 1, JANUARY 2016 Add to Reading List Source URL: www.eecs.qmul.ac.uk Language: English - Date: 2016-03-10 11:23:54 Cache CPU cache Centrality Distributed cache Draft:Cache memory
15	Design of Parallel and High Performance Computing HS 2013 Markus P¨ uschel, Torsten Hoefler Department of Computer Science ETH Zurich Add to Reading List Source URL: spcl.inf.ethz.ch Language: English - Date: 2013-10-10 09:58:44 Cache coherency MESI protocol Cache coherence Cache False sharing Draft:Cache memory CPU cache
16	An Operational Semantics of Cache Coherent Multicore Architectures∗ Shiji Bijo, Einar Broch Johnsen, Ka I Pun, and S. Lizeth Tapia Tarifa University of Oslo, Norway {shijib, einarj, violet, sltarifa}@ifi.uio.no Add to Reading List Source URL: einarj.at.ifi.uio.no Language: English - Date: 2016-01-07 10:39:37 Cache coherency Parallel computing Computer architecture Computer memory computing CPU cache MSI protocol Coherent cache Cache MESI protocol Multi-core processor Draft:Cache memory
17	Reducing Capacity and Conflict Misses using Set Saturation Levels Dyer Rol´an, Basilio B. Fraguela and Ram´on Doallo Grupo de Arquitectura de Computadores Departamento de Electr´onica e Sistemas Universidade da Coru˜ Add to Reading List Source URL: www.des.udc.es Language: English - Date: 2011-06-03 07:07:22 Cache Central processing unit Computer architecture Computer memory CPU cache Virtual memory Cache algorithms Thrashing DSBC Memory hierarchy Microarchitecture Draft:Cache memory
18	Insight into Application Performance Using Application-Dependent Characteristics Waleed Alkohlani1 , Jeanine Cook2 , and Nafiul Siddique1 1 Klipsch School of Electrical and Computer Engineering, Add to Reading List Source URL: www.dcs.warwick.ac.uk Language: English - Date: 2014-11-13 12:51:32 Cache Central processing unit Computer memory Computer architecture Parallel computing CPU cache Locality of reference Benchmark Microarchitecture Instruction set Instruction-level parallelism Draft:Cache memory
19	HexPADS: a platform to detect “stealth” attacks Mathias Payer Purdue University Abstract. Current systems are under constant attack from many different sources. Both local and remote attackers try to escalate their p Add to Reading List Source URL: hexhive.github.io Language: English - Date: 2016-06-13 11:08:40 Computer memory Computer architecture Central processing unit Cache CPU cache Parallel computing Row hammer Dynamic random-access memory Shared memory Microarchitecture Draft:Cache memory Cold boot attack
20	Architectural Support for Software-Defined Metadata Processing Udit Dhawan1 C˘at˘alin Hri¸tcu2 Raphael Rubin1 Nikos Vasilakis1 Jonathan M. Smith1 Add to Reading List Source URL: ic.ese.upenn.edu Language: English - Date: 2015-01-14 09:16:42 Computer memory Cache Computing Computer hardware Central processing unit Computer architecture Computer engineering CPU cache Locality of reference Draft:Cache memory

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